1. Technology Field
The present invention relates to a flash memory control circuit, a flash memory storage system, and a data transfer method, wherein the usage of a buffer memory is effectively reduced and the time for writing data into a flash memory is effectively shortened.
2. Description of Related Art
The consumers' demand to storage media has increased drastically along with the widespread of digital cameras, cell phones, and MP3 in recent years. Flash memory is one of the most adaptable memories for such battery-powered portable products due to its characteristics such as data non-volatility, low power consumption, small volume, and non-mechanical structure. A solid state drive (SSD) is a storage device which uses a NAND flash memory as its storage medium.
A flash memory in a flash memory storage device has a plurality of physical blocks, and each of the physical blocks has a plurality of pages, wherein data is written into a physical block according to the sequence of these pages.
Generally speaking, the process for writing data into a page can be divided into a data transferring phase and a data programming phase. To be specific, when data is to be stored into a page of a flash memory, a control circuit of the flash memory storage device transfers the data into a buffer area of the flash memory. Then, the flash memory programs the data from the buffer area into the page. The flash memory is in a busy status when it programs the data into the page. The control circuit cannot give any command or transfer any data to the flash memory when the flash memory is in the busy status.
In addition, a flash memory can be categorized as a single level cell (SLC) NAND flash memory or a multi level cell (MLC) NAND flash memory according to the number of bits which each memory cell can store. The physical blocks in a MLC NAND flash memory are programmed in multiple phases. Taking a 2-level cell NAND flash memory as an example, the physical blocks thereof are programmed in 2 phases. During the first phase, data is written into lower pages, wherein the physical characteristic of a lower page is similar to that of a SLC NAND flash memory. After the first phase, data is written into upper pages, wherein the write speed of the lower pages is faster than that of the upper pages. Similarly, in an 8-level cell NAND flash memory or a 16-level cell NAND flash memory, each memory cell has more pages and accordingly data is written into these memory cells in more phases.
Conventionally, in order to increase the write speed of a flash memory storage device, multiple flash memories are usually disposed in the flash memory storage device and data is written into these flash memories in an interleaving manner. Taking a flash memory storage device disposed with a first flash memory and a second flash memory as an example, when a host system is about to write a plurality of page data (i.e., data greater than 1 page) into the flash memory storage device, the control circuit transfers one of the page data to the first flash memory. When the first flash memory is in the busy status, the control circuit transfers another page data to the second flash memory. After that, when the second flash memory is in the busy status, the control circuit transfers yet another page data to the first flash memory. As described above, the control circuit transfers the page data to the first flash memory and the second flash memory in an interleaving manner, so that the time for writing the page data is shortened. In foregoing example of the MLC NAND flash memory, when the page data is being written into the upper pages of the first flash memory and the second flash memory (i.e., the first flash memory and the second flash memory are on the busy status), the control circuit has to wait for a long time (i.e., until the data writing process to one of the first flash memory and the second flash memory is completed) before it can continue to transfer data to the first flash memory or the second flash memory. During this period, the host system continues to transfer data to the flash memory storage device. Accordingly, a buffer memory has to be disposed in the flash memory storage device for temporarily storing the data transferred by the host system. Along with the increase in the number of levels of a MLC NAND flash memory, the time for programming some pages is prolonged so that a buffer memory with greater capacity has to be disposed.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.